You can use the CLOCK_LOW_FANOUT constraint to contain the loads of a clock buffer in a single clock region. You can set the CLOCK_LOW_FANOUT constraint on a clock net segment directly driven by a global clock buffer or on a list of flip-flops.
Constraint Example for Flip-Flops
Setting the CLOCK_LOW_FANOUT constraint on a list of flip-flops
driven by a global clock buffer causes opt_design
to create a new parallel global clock buffer to isolate the flip-flops. During
place_design, the isolated flip-flops that are
driven by the newly created parallel global clock buffer are contained to a single
clock region.
set_property CLOCK_LOW_FANOUT TRUE [get_cells safeClockStartup_reg[*]]In the design, an always-on clock network initially drives more than
2000 loads, including the flip-flops that are part of the clock gating
synchronization circuit used to clock gate other logic. The following schematics
show the clock gating synchronization circuit and additional logic connected to the
always-on clock network before and after opt_design
creates a new parallel global clock buffer to isolate the clock gating
synchronization circuit.
The Device window of the fully implemented design shows the clock gating synchronization circuit with green markers along with the always-on logic and clock-gated logic. The clock gating synchronization circuit is placed in a CLOCK_REGION that results in the minimal insertion delay from the BUFG in the XPIO.
Constraint Example for Clock Nets Driven by an XPIO Global Clock Buffer
If you set the CLOCK_LOW_FANOUT property on a clock net segment directly driven by a global clock buffer in an XPIO CLOCK_REGION and the fanout of the global clock buffer is less than 2000 loads, the placement of the loads is contained to a single clock region.
The following example shows the CLOCK_LOW_FANOUT constraint applied to the clock net segment directly driven by a global clock buffer placed in the XPIO. The input clock port, clkIn has a PACKAGE_PIN assignment to a GCIO located in the XPIO CLOCK_REGION X2Y0 and drives a DPLL. The DPLL drives a global clock buffer that subsequently drives the clock network with 128 loads. The loads of the global clock buffer are all placed in the CLOCK_REGION X1Y1.
# PACKAGE_PIN BB44 - High Performance XPIO IOBank 702 - CLOCK_REGION X2Y0
set_property PACKAGE_PIN BB44 [get_ports clkIn]
set_property IOSTANDARD SSTL12 [get_ports clkIn]
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins BUFG_clkout1_inst/O]]
Constraint Example for Clock Nets Driven by an HDIO Global Clock Buffer
If you set the CLOCK_LOW_FANOUT property on a clock net segment directly driven by a global clock buffer in an HDIO CLOCK_REGION and the fanout of the global clock buffer is less than 2000 loads, the placement of the loads is contained to the same CLOCK_REGION as the global clock buffer.
The following example shows the CLOCK_LOW_FANOUT constraint applied to the clock net segment directly driven by a global clock buffer placed in the HDIO. The input clock port, clkIn has a PACKAGE_PIN assignment to a GCIO located in the HDIO CLOCK_REGION X0Y4 and drives a DPLL. The DPLL drives a global clock buffer that subsequently drives the clock network with 128 loads. The loads of the global clock buffer are all placed in the CLOCK_REGION X0Y4.
# PACKAGE_PIN L35 - High Density HDIO IOBank 306 - CLOCK_REGION X0Y4
set_property PACKAGE_PIN L35 [get_ports clkIn]
set_property IOSTANDARD LVCMOS33 [get_ports clkIn]
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins BUFG_clkout1_inst/O]]