The CLOCK_DEDICATED_ROUTE constraint is typically used when driving from a clock buffer in one clock region to an MMCM/XPLL/DPLL in another clock region. By default, the CLOCK_DEDICATED_ROUTE constraint is set to TRUE, and the buffer-MMCM/XPLL/DPLL pair must be placed in the same clock region.
The following table summarizes the different CLOCK_DEDICATED_ROUTE constraint values, use, and behavior.
| Value | Use | Behavior |
|---|---|---|
| TRUE | Default value on clock nets |
Global clock buffer and MMCM/XPLL/DPLLs must be placed in the same clock region. This value ensures the net is routed using only global clock resources. |
| SAME_CMT_COLUMN |
Net driven by a BUFG_GT global clock buffer or a global clock buffer in an HDIO bank Examples: |
DPLLs must be placed in a clock region in the same vertical column. This value ensures the net is routed using only global clock resources. For optimal results, Xilinx recommends using a LOC constraint on the DPLL to control placement of the DPLL within in the same vertical column. |
| SAME_CMT_ROW |
Net driven by a global clock buffer
Examples: |
MMCM/XPLL/DPLLs can be placed in any horizontal clock region row with available resources. This value ensures the net is routed using only global clock resources. For optimal results, Xilinx recommends using a LOC constraint on the MMCM/XPLL/DPLL to control placement of the MMCM/XPLL/DPLL within the horizontal clock region row of the device. |
| ANY_CMT_REGION |
Net driven by a global clock buffer
Examples: |
MMCM/XPLL/DPLLs can be placed in any clock region with available resources. This value ensures the net is routed using only global clock resources. For optimal results, Xilinx recommends using a LOC constraint on the MMCM/XPLL/DPLL to control placement of the MMCM/XPLL/DPLL within the device. |
| FALSE |
Clock net not driven by a global clock buffer but part of the clock network (for example, nets driven by the output of an IBUF or nets directly connected to output clock pins of an MMCM)
Examples: |
Net is routed using fabric and global clock resources. This can adversely affect the timing characteristics of the clock network, such as jitter and skew. Important: For Versal devices, FALSE must only be used when a clock
normally routed with global clock resources needs to be routed with
fabric resources for special design reasons.
|
Driving MMCMs/XPLLs/DPLLs Between Row-Aligned XPIO Clock Regions
When driving from a clock buffer in one XPIO clock region to an MMCM/XPLL/DPLL in a row-aligned XPIO clock region that is not adjacent, you must set the CLOCK_DEDICATED_ROUTE constraint to SAME_CMT_ROW. This prevents implementation errors and ensures that the clock is routed with global clock resources throughout the XPIO clock regions. The following example and figure show a clock buffer driving two DPLLs in non-adjacent XPIO clock regions.
set_property CLOCK_DEDICATED_ROUTE SAME_CMT_ROW [get_nets -of [get_pins BUFG_inst/O]]
set_property LOC DPLL_X4Y0 [get_cells DPLL_inst_1]
set_property LOC DPLL_X11Y0 [get_cells DPLL_inst_2]
Driving DPLLs Between Clock Regions Not Row-Aligned
For devices in which the DPLL is available in the HDIO, you must set the CLOCK_DEDICATED_ROUTE constraint to ANY_CMT_REGION in the following cases:
- When driving from a clock buffer in an XPIO clock region to a DPLL in an HDIO clock region
- When driving from a clock buffer in an HDIO clock region to an MMCM/XPLL/DPLL in an XPIO clock region
This prevents implementation errors and ensures that the clock is routed with global clock resources throughout the device. The following example shows a clock buffer from an XPIO clock region driving two DPLLs where one DPLL is in an XPIO clock region and the other DPLL is in an HDIO clock region.
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_REGION [get_nets -of [get_pins BUFG_inst/O]]
set_property LOC DPLL_X4Y2 [get_cells DPLL_inst_1]
set_property LOC DPLL_X12Y0 [get_cells DPLL_inst_2]