USER_CLOCK_ROOT assignment in Versal ACAP differs slightly from UltraScale devices due to changes in the clocking architecture. In Versal ACAP, not all clock regions have a vertical clock spine, and these clock regions cannot be used for USER_CLOCK_ROOT assignment.
The following figure shows the locations of the vertical clock spines. The clock spines highlighted in blue are adjacent to the vertical NoC column at the boundary of two clock regions. The Vivado tools only allow the USER_CLOCK_ROOT to be set to the left clock region of these clock spines. The vertical clock spines in the transceiver Quad columns on the left and right side of the device are highlighted in purple. A USER_CLOCK_ROOT can be assigned to any clock region in the transceiver Quad columns. However, assigning a USER_CLOCK_ROOT to a clock region in the leftmost transceiver Quad column (above the PS) blocks the clock from reaching any loads to the right of the PS. In addition, clocks sourced from XPIO cannot have their USER_CLOCK_ROOT assigned to the leftmost transceiver Quad column above the PS. The clock regions highlighted in green indicate legal USER_CLOCK_ROOT assignments, and the clock regions in red indicate illegal clock root assignments.
In the following example, the USER_CLOCK_ROOT constraint is illegal, because the constraint is set to the clock region to the right of the vertical clock spine:
set_property USER_CLOCK_ROOT X4Y3 [get_nets -of [get_pins BUFGCE_DIV_inst/O]]In this case, the placer issues a message and assigns a legal CLOCK_ROOT to the net such as CLOCK_REGION X3Y3.
In addition to the general USER_CLOCK_ROOT rules listed above for Versal SSI technology devices, any clock spanning more than one SLR must have a clock root located on the clock region row just below a SLR boundary. If the USER_CLOCK_ROOT constraint is set to any other clock region, the placer will ignore the constraint to create a balanced clock tree and minimize clock skew.
