Running Report Methodology

Running Report Methodology - 2022.2 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID

UG1387

Release Date

2022-11-16

Version

2022.2 English

The Vivado tools provide a Methodology Report that specifically checks for compliance with methodology. The tools run different checks depending on the stage of the design process:

RTL design: RTL lint-style checks
Synthesized and implemented designs: Netlist, constraints, and timing checks

In Project Mode, the tools automatically run Report Methodology during implementation (opt_design or route_design) by default. To run these checks manually, use either of the following methods:

At the Tcl prompt, open the design to be validated, and enter following Tcl command: report_methodology
To run these checks from the Vivado IDE, open the design to be validated, and select Reports > Report Methodology.

Recommended: To identify common design issues, run this report the first time you synthesize the design. Run this report again after significant module additions, constraint changes, or clocking circuit changes.

Note: For Xilinx® -supplied IP cores, the violations are already reviewed and checked.

Any violations are listed in the Methodology window, as shown in the following figure. If a specific methodology violation does not need to be fixed, make sure that you understand the violation and its implication clearly and why the violation does not negatively impact your design.

Important: You must resolve all Critical Warnings and most Warnings to ensure good QoR, timing analysis accuracy, and reliable hardware stability are met. For details, see this link in the Versal ACAP System Integration and Validation Methodology Guide (UG1388). For methodology check violations that can be safely ignored, you can use the waiver mechanism to waive the violations. For details, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Note: Methodology checks related to RAMB and DSP primitive optional pipelining (SYNTH-6, SYNTH-11, SYNTH-12 and SYNTH-13) are not reported when setup timing is greater than 1 ns on all of the input or output paths for the primitives.

Figure 1. Methodology Window

For more information on running Report Methodology, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895). Also, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).