The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/16/2022 Version 2022.2 | |
| Throughout document | Changed performance to maximum frequency. |
| System Design Types | Updated System Design Types figure and removed no/custom platform. |
| Design Flow Diagrams | Updated Traditional Design Flow for Versal Devices figure. |
| Traditional Design Flow for Embedded Systems | Updated AI Engine important note. |
| Design Planning Considerations for Classic SoC Boot | Added parameter control note. |
| Auto-Pipelining Considerations | Updated XDC constraints code block. |
| Low Fanout Clocks | Added new section. |
| Using the GCLK_DESKEW Property on a Clock Net | Clarified calibrated deskew description. |
| Using the CLOCK_LOW_FANOUT Constraint | Updated HDIO CLOCK_LOW_FANOUT Example in the Device Window and Schematic Window figure. |
| USER_CLOCK_ROOT Assignment | Added USER_CLOCK_ROOT SSI technology description and figure. |
| XPIO Global Clock Buffer Clock Enable Timing | Added HARDSYNC note. |
| Gigabit Transceivers (GTs) | Added clock resource balancing note. |
| Corner Banks | Added new section. |
| Defining Power and Thermal Constraints | Updated to Power Design Manager. |
| Incremental Synthesis | Added incremental implementation flows description. |
| Using Incremental Implementation Flows | Added SSI note, removed Incremental Implementation Flow Modes, and removed High and Low Reuse Modes sections. |
| Configuring the Incremental Flow | Added new section. |
| Compile Time Considerations | Removed low reuse mode. |
| 05/25/2022 Version 2022.1 | |
| Design Flow Diagrams | Added new section. |
| Platform-Based Design Flow Best Practices | Added table. |
| Design Planning Considerations for DFX based Vitis Acceleration Platform Development | Added new section. |
| Design Planning Considerations for Classic SoC Boot | Added new section. |
| Design Planning Considerations for Tandem Configuration | Added new section. |
| Defining a Good Block Design Hierarchy | Added new section. |
| Instantiating Block Designs | Added benefits of each approach. |
| Using Different Source Files in IP Integrator | Added design hierarchy diagrams for each section. |
| Recommendations for Designing with Versal Device IP | Added new section. |
| Recommendations for Different Versal Device Design Topologies | Added new section. |
| Checking for Feedback Structures in Registers | Updated example. |
| Check Inferred Logic | Added information on retiming_forward and retiming_backward. |
| XPIO Global Clock Buffer Clock Enable Timing | Added new section. |
| Boundary Clock Nets | Removed example. |
| SSI Technology Considerations for I/O Planning | Added new section. |
| Designing with SSI Devices | Added new chapter. |
| Using the Boundary Logic Interface Constraint | Added new section. |
| Floorplanning Constraints for Dynamic Function eXchange | Added recommendations and revised entire section. |
| Assessing Post-Synthesis Quality of Results | Updated table. |
| NoC Compiler Runs During Placement | Added information on global placement. |