Reconfigurable Module Internal Clock Nets - 2022.2 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2022-11-16
Version
2022.2 English

In a reconfigurable module (RM) internal clock net, the clock root is placed at the center of the loads inside the reconfigurable partition (RP) Pblock. This clock root placement offers more flexibility for placement and routing of the RM internal clock in subsequent implementations. Xilinx recommends this approach whenever possible to achieve better skew and optimal clock root placement.