Vivado Design Suite logic optimization optimizes
the current in-memory netlist. Because this is the first view of the assembled design
(RTL and IP blocks), the design can usually be further optimized. By default the opt_design command performs logic trimming, removing of
cells with no loads, propagating constant inputs, and block RAM power optimization. It
also optionally performs other optimizations such as remap, which combines LUTs in
series into fewer LUTs to reduce path depth.