High fanout nets are much easier to deal with early in the design process. What
constitutes too high of a fanout is often dictated by the target clock frequency
requirements and the construction of the paths. You can use the following techniques to
address issues with high fanout nets.
Recommended: Identify high fanout nets using the
report_high_fanout_nets Tcl command after synthesis.
Monitor the impact of these nets on design timing closure as you progress through
the implementation process.