A commonly used pipelining technique is to identify a large combinatorial logic path, break it into smaller paths, and introduce a register stage between these paths, ideally balancing each pipeline stage.
To determine whether a design requires pipelining, identify the frequency of the clocks and the amount of logic distributed across each of the clock groups. You can use the report_design_analysis Tcl command with the -logic_level_distribution option to determine the logic-level distribution for each of the clock groups.
Tip: The design analysis report also highlights the number of paths with zero logic levels, which you can use to determine where to make modifications in your code.