Clock enables are created when an incomplete conditional statement is coded into a synchronous
block. A clock enable is inferred to retain the last value when the prior conditions are
not met. When this is the desired functionality, it is valid to code in this manner.
However, in some cases when the prior conditional values are not met, the output is a
don't care. In that case, Xilinx recommends closing off the
conditional (that is, use an else clause), with a defined constant
(that is, assign the signal to a one or a zero).
In most implementations, this does not result in added logic, and avoids the need for a clock enable. The exception to this rule is in the case of a large bus when inferring a clock enable in which the value is held can help in power reduction. The basic premise is that when small numbers of registers are inferred, a clock enable can be detrimental because it increases control set count. However, in larger groups, it can become more beneficial and is recommended.