Target Architecture - 2022.2 English

Vitis Networking P4 User Guide (UG1308)

Document ID
UG1308
Version
2022.2 English
Revision

The P4 architecture defines the P4-programmable components and the data plane interfaces between them. The P416 specification has architecture-language separation: this gives target providers the flexibility to describe the nature of the P4-programmable components within their own packet processing architectures. This architecture description gives signatures for container holes that P4 developers can fill with their desired functionality. The containers are specified in a generic fashion to maintain P4's protocol independence. Xilinx's Vitis™ Networking P4 compiler supports the Vitis Networking P4 architecture that developers can target.

Designs targeting the Vitis Networking P4 architecture generate a pipeline with three customizable engines. The following figure shows how the engines are connected within the pipeline. The interfaces are defined generically, which allows developers the flexibility to define how much header and control data is passing through the system.

Figure 1. Xilinx P4 Top-Level Vitis Networking P4 Design

The first engine (Parser) is a parsing block that extracts headers from the packet. The next engine (Match-Action), is a control block that can be used to modify header and control data. The last engine (Deparser) is another control block specifying the order that headers should be deparsed back into the packet.

User-defined metadata ports are provided at the input and output to/from the Vitis Networking P4 design. These ports are user-defined structures associated with each packet based on the definition from the user’s P4 program. Standard metadata generated during the execution of the P4 program is also available to the user – this metadata is provided by the architecture associated with each packet.

User extern ports are provided in the Vitis Networking P4 design, for user externs created in the user's P4 program. User externs themselves are instantiated outside the Vitis Networking P4 instance.

AXI4-Lite memory-mapped ports are used for configuration and control of the Look-up engines and user externs.

An example of P4-programmed components for this architecture is provided in Nulling Blocks: Sample P416 Program.

If multiple consecutive functions are required (more than one parsing function for example), multiple serial instances of Vitis Networking P4 IPs are a supported configuration. Similarly, if parallel processing of packet streams is required, Vitis Networking P4 instances can be deployed in parallel.

Although Vitis Networking P4 architecture requires all three blocks (Parser, Match-Action, and Deparser) to be present, it is possible to 'null' some blocks to focus on the blocks of interest - for example, parsing to create some metadata output without performing any other packet modifications. An example of nulling blocks is provided in Nulling Blocks.