Table Programming - 2022.2 English

Vitis Networking P4 User Guide (UG1308)

Document ID
UG1308
Version
2022.2 English
Revision

There are a few common pitfalls related to table programming:

  • It is important to always re-compile the software drivers following any changes to the P4 program. This includes using the re-generated *_defs.c/*_defs.h files.
  • It is important to always re-compile the software drivers following an upgrade to a different version of VitisNetP4.
  • The 32-bit register read/write functions must be defined for the target design setup (see Porting to Platform section of Chapter 5: Runtime Drivers for details). This should include any base addressing to the beginning of the VitisNetP4 instance.
  • The AXI-Lite address width is dependent on the number of control-plane elements in the P4 design (e.g. the number of tables). If the P4 program is changed after the AXI-Lite interface connections have been made in the hardware design, then it is possible that a wider AXI-Lite address width and address space is required (e.g. if new tables were added to the P4 program, or if the statistics registers are enabled). In some cases the Address Editor or AXI Interconnect needs to be updated to account for an increase in address space, or else some of the tables may not be accessible for programming.