Register Map - Register Map - 2022.2 English

The Vitis Networking P4 IP register map can be found in the generated file, <inst_name>_defs.h. See the Generated Files sub-section in the Vitis Networking P4 Tool Flows chapter for the path to this generated file. The memory contents of the TinyBCAM/TinyTCAM and Direct tables can be updated by means of AXI4-Lite accesses, that of the CAMs cannot. The CAM's updates are handled by the CAM driver. The Tiny CAM and Direct table AXI4-Lite interfaces support read and write operations to add, update and delete table entries. The register maps are shown in the following table.

The register map of the Counter Externs is also found in this section.

Table 1. Direct Tables Register Map
Register Offset	Bit Range	Description
0x00	[31:0]	Control Register: RD flag (bit 0): when asserted, a read operation is triggered. Automatically cleared when the read has completed and data is available in the data register(s). WR flag (bit 1): when asserted, a write operation is triggered. Automatically cleared when the write has completed. Debug mode (bit 29): ‘0’ = allows normal use of the table entry read/write registers. ‘1’ = will cause the table entry read/write registers to be updated automatically with every data plane lookup operation. Debug captured (bit 30): ‘1’ = indicates that a data plane lookup has occurred while debug mode was enabled such that the details are captured in the table entry read/write registers. ‘0’ = no data plane lookup operations have been captured yet. Hit/miss flag (bit 31): must be set to 1 when an entry is added or updated and set to 0 when an entry is deleted. Read and Write access. In debug mode, this register will automatically be updated with each data plane lookup to reflect the hit/miss status. Default value: 0. Bits from 2 to 28 are reserved.
0x04	[31:0]	Address Register. This register must be updated prior to the assertion of a read or write flag. In debug mode, this register will automatically be updated with each data plane lookup key.
0x08	[31:0]	ECC Control Register [0]: Inject Single-bit error [1]: Inject Double-bit error [2]: Disable ECC Scrubbing [31]: ECC Enable (read-only) All other bits are reserved.
0x0C	[31:0]	Lookup count. Clear on read.
0x10	[31:0]	Hit count. Clear on read.
0x14	[31:0]	Miss count. Clear on read.
0x18	[31:0]	Single bit error count. Clear on read.
0x1C	[31:0]	Double bit error count. Clear on read.
0x20	[31:0]	Last ECC errored address (Single-bit error).
0x24	[31:0]	Last ECC errored address (Double-bit error)
0x28-0x3F	[31:0]	Reserved
0x40	[31:0]	Data Register (part 1). This register must be updated prior to the assertion of the write flag. The contents of this register are automatically updated after a read operation. In debug mode, this register will automatically be updated with the response value for any data plane lookup hit. If RESPONSE_WIDTH value is greater than 32 bits, consecutive registers need to be used. This set of registers extend to the required total response width.
0x44	[31:0]	Data register (part 2).
...	[31:0]	...
0x1FFC	[31:0]	Data register (part 2032).

Table 2. TinyBCAM/TinyTCAM Register Map
Register Offset	Bit Range	Access	Description
0x00	[31:0]	RW	Control Register: RD flag (bit 0): when asserted, a read operation is triggered. Automatically cleared when the read has completed and the data is available in the data register(s). WR flag (bit 1): when asserted, a write operation is triggered. Automatically cleared when the write has completed. Debug mode (bit 29): ‘0’ = allows normal use of the table entry read/write registers. ‘1’ = will cause the table entry read/write registers to be updated automatically with every data plane lookup operation. Debug captured (bit 30): ‘1’ = indicates that a data plane lookup has occurred while debug mode was enabled such that the details are captured in the table entry read/write registers. ‘0’ = no data plane lookup operations have been captured yet.Reset flag (bit 2): when asserted, all CAM entries in a table are reset. EntryInUse flag (bit 31): must be set to 1 when an entry is added or updated and set to 0 when an entry is deleted. Read and Write access. In debug mode, this register will automatically be updated with each data plane lookup to reflect the EntryInUse status. Default value: 0. Bits from 2 to 28 are reserved.
0x04	[31:0]	RW	Entry ID. This register must be updated prior to the assertion of a read or write flag. Note: The Entry ID equals the entry position in the table. In debug mode, this register will automatically be updated with each data plane lookup hit to reflect the corresponding Entry ID.
0x08	[31:0]	RO	Emulation Mode Register: Used by Software to confirm correct TinyCAM driver is instantiated i.e. TinyBCAM or TinyTCAM driver.
0x0C	[31:0]	RO	Lookup count. Clear-on-read.
0x10	[31:0]	RO	Hit count. Clear-on-read.
0x14	[31:0]	RO	Miss count. Clear-on-read.
0x18-0x3f	[31:0]	RO	Reserved.
0x40	[31:0]	RW	Data Register (part 1). This register must be updated prior to the assertion of the write flag. The contents of this register are automatically updated after a read operation. In debug mode, this register will automatically be updated with the key value for each data plane lookup request. The response value will only be updated if there is a hit. If the ENTRY_WIDTH value is greater than 32 bits, then consecutive registers need to be used. This set of registers extend to the required total response width.
0x44	[31:0]	RW	Data Register (part 2).
...	[31:0]	RW	...
0x1FFC	[31:0]	RW	Data Register (part 2032).

Table 3. Counter Extern Register Map
Register Offset	Bit Range	Access	Description
0x00	[31:0]	RW	Control - a read/write operation is initiated with each write to this register: [24] Write Enable 1: Write Operation 0: Read Operation [22:16] Burst Size: This field contains the burst size minus 1 e.g. value of 0 corresponds to burst size of 1 [15:0] Start Address
0x04	[31:0]	R0	Status [0] Burst in progress flag
0x08	[31:0]	RW	ECC Control [4] ECC Scrub Disable [3] Collection RAM Injectdbiterr [2] Collection RAM Injectsbiterr [1] Counter RAM Injectdbiterr [0] Counter RAM Injectsbiterr
0x0C	[31:0]	RW	Read Mode Control [0] Disable Clear-on-Read 1: Read without clear 0: Clear on read (default)
0x10	[31:0]	RW	ECC Single Bit Error Count
0x14	[31:0]	RW	ECC Double Bit Error Count
0x20	[31:0]	RW	Write Value LSB: Least Significant half of counter write value [31:0]
0x24	[31:0]	RW	Write Value MSB: Most Significant half of counter write value [63:32]
0x800	[31:0]	RO	Collection RAM: Counter value (least significant half)
0x804	[31:0]	RO	Collection RAM: Counter value (most significant half)
0x808...	[31:0]	RO	Collection RAM...

The Statistics and Control register map can be found in the generated file, <inst_name>_defs.h. See the Generated Files sub-section in the Vitis Networking P4 Tool Flows chapter for the path to this generated file.

The Statistics and Control Register AXI4-Lite interface supports read and write operations for these registers. This includes Interrupt Registers in relation to ECC errors. These registers are split into “IP Components” (which are specific to the target architecture) and “P4 Elements” (which correspond to tables and counter externs in the P4 program). For each component/element, there are 2 register bits to distinguish between ECC Single-bit and Double-bit error functionality. The ECC Capabilities registers indicate which components/elements support ECC functionality since this is not always obvious – it can be dictated by the RAM-style setting which is sometimes automatically determined by the tool, e.g. there is no ECC supported when targeting Distributed RAM.

Table 4. Statistics and Control Register Map
Register Offset	Bit Range	Reset Value	Access	Description
Configuration Registers
0x000	[31:0]		Read-only	VitisNetP4 Version (SDNV) [31:24]: Reserved [23:16]: IP Core Revision number [15:8]: IP Core Minor Version number [7:0]: IP Core Major Version number
0x004	[31:0]		Read-only	VitisNetP4 Instance Configuration (SDNC) [31:30]: Reserved [29:20]: AXI Stream Clock in MHz [19:10]: CAM Memory Clock in MHz [9:0]: Packet Rate in Mp/s
0x008	[31:0]		Read-only	ECC Capabilities Register for IP Components (IP_ECCC) Bit indexing is allocated as follows: Bit[0]: Packet FIFO ECC Single-bit Error Functionality Bit[1]: Packet FIFO ECC Double-bit Error Functionality Bit[2]: Metadata FIFO ECC Single-bit Error Functionality Bit[3]: Metadata FIFO ECC Double-bit Error Functionality Bits[31:4]: Reserved The values of each bit have the following meaning: 1: ECC is supported for this element/component 0: ECC is not supported for this element/component
0x00C	[2n-1:0]		Read-only	ECC Capabilities Register for P4 Elements (P4_ECCC) Bit indexing is allocated as follows for all tables and counter externs (up to max n=128) in the P4 program, where m is the number of tables: Bit[0]: First Table ECC Single-bit Error Functionality Bit[1]: First Table ECC Double-bit Error Functionality Bit[2]: Second Table ECC Single-bit Error Functionality Bit[3]: Second Table ECC Double-bit Error Functionality … Bit[2m-2]: m’th Table ECC Single-bit Error Functionality Bit [2m-1]: m’th Table ECC Double-bit Error Functionality Bit [2m]: First Counter Extern ECC Single-bit Error Functionality Bit [2m+1]: First Counter Extern ECC Double-bit Error Functionality ... Bit [2n-2]: (n-m)’th Counter Extern ECC Single-bit Error Functionality Bit [2n-1]: (n-m)’th Counter Extern ECC Double-bit Error Functionality The values of each bit have the following meaning: 1: ECC is supported for this element/component 0: ECC is not supported for this element/component
Interrupt Registers
0x400 0x404	[31:0] [2n-1:0]	0x0	Read-only	Interrupt Status Register (ISR) The bit indexing aligns with the IP_ECCC and P4_ECCC registers above. The values of each bit have the following meaning: 1: Pending interrupt 0: Interrupt cleared
0x424 0x428	[31:0] [2n-1:0]	0x0	Read/Write	Interrupt Enable Register (IER) The bit indexing aligns with the IP_ECCC and P4_ECCC registers above. The values of each bit have the following meaning: 1: Interrupt enabled 0: Interrupt disabled
0x448 0x44C	[31:0] [2n-1:0]	0x0	Clear-on-Write	Interrupt Clear Register (ICR)The bit indexing aligns with the IP_ECCC and P4_ECCC registers above. The values of each bit have the following meaning: 1: Clear interrupt 0: Ignored
Error Registers
0x1018	[31:0]	0x0	Clear-on-Read	Packet FIFO Single-bit ECC Error Counter (PFSE)
0x101C	[31:0]	0x0	Clear-on-Read	Packet FIFO Double-bit ECC Error Counter (PFDE)
0x1020	[31:0]	0x0	Clear-on-Read	Vector FIFO Single-bit ECC Error Counter (VFSE)
0x1024	[31:0]	0x0	Clear-on-Read	Vector FIFO Double-bit ECC Error Counter (VFDE)
Control Registers
0x1400 0x1404	[31:0] [2n-1:0]	0x0	Read/Write	Inject ECC Bit Error Register (IEBE)The bit indexing aligns with the IP_ECCC and P4_ECCC registers above. The values of each bit have the following meaning: 1: Start injecting ECC errors 0: Stop injecting ECC errors
0x1424	[31:0]	0xFFFF	Read/Write	Packet Rate Limiter Margin (PRLM) [31:16]: Reserved [15:0]: Maximum number of packets per 1000 AXIS clock cycles

Register Map - Register Map - 2022.2 English - UG1308

Vitis Networking P4 User Guide (UG1308)