Simulations should be run as normal for any IP block once the RTL output for the design has been generated. For information on running simulations on the Vivado Design Suite project, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
Simulations should be run as normal for any IP block once the RTL output for the design has been generated. For information on running simulations on the Vivado Design Suite project, see the Vivado Design Suite User Guide: Logic Simulation (UG900).