The rest of this user guide is organized as follows:
- Chapter 2, Target Architecture describes the Vitis Networking P4 Architecture supported by the Vitis Networking P4 Tool.
- Chapter 3, Vitis Networking P4 Tool Flow describes the top-level interface signals and clocking.
- Chapter 4, Vitis Networking P4 Tool Interface describes the Software and Hardware tool flows for Vitis Networking P4 designs.
- Chapter 5, Runtime Drivers describes the driver software released with the Vitis Networking P4 tool.
- Chapter 6, Examples of Basic Architectures illustrates examples of how Vitis Networking P4 can be used.
- Appendix A provides a sample P416 program.
- Appendix B identifies supported P416 language features.
- Appendix C provides example nulling blocks.
- Appendix D provides P4 references and guidelines.
- Appendix E describes DPI and its use in the example designs.
- Appendix F identifies additional resources and legal notices.
- Appendix G includes details about debugging tools.
- Appendix H provides information on Xilinx Resources and document references.