History of P4 and Vitis Networking P4 - 2022.2 English

Vitis Networking P4 User Guide (UG1308)

Document ID
UG1308
Version
2022.2 English
Revision

P4 is a language standard for describing programmable data planes that can target a wide range of technologies including CPUs, FPGAs, and NPUs. The initial language specification called P414 was released in early 2015. Limitations were quickly identified and the community began exploring new features. The new P416 specification was released in May, 2017. The Xilinx® Vitis™ Networking P4 solution described here targets P416.

The P4 language is target independent by design. The specification outlines most of the expected behavior, but to accommodate different target platforms some behavior is defined as architecture-specific (such as table properties and extern objects). The expectation is that each target compiler back-end can define its own level of support in these specific cases.

The Xilinx Vitis Networking P4 (VitisNetP4) high-level design environment has been created to simplify the design of packet-processing data planes that target FPGA hardware. VitisNetP4 is a tool to convert the P4 design intent into a Xilinx FPGA design solution. VitisNetP4 allows programmers to build new data planes by explicitly specifying the header and packet processing. VitisNetP4 processing engines have specialized behavior and include: parsing engines, match-action engines, and deparsing engines, each generated according to an application-specific requirement. To implement a P4 design the compiler maps the control flow onto a custom data plane architecture of VitisNetP4 engines. This mapping chooses appropriate engine types and customizes each of them based on the P4-specified processing.

Vitis Networking P4 features the following:

  • Construction of hierarchical Vitis Networking P4 systems, consisting of a large variety of different types of engines including: Parsing, Deparsing, and Match-Action engines.

    • Parsing engines extract header information from packets.
    • Deparsing engines manipulate the contents of packet headers by inserting, modifying, or removing packet data.
    • Action engines are designed for manipulating metadata that might be determined from packets or data originating externally or internally from some other engine.

    • Look-up engines instantiate memory search IP cores generated from a library for packet processing including: exact match (BCAM), longest-prefix match (STCAM), ternary match (TCAM), and RAM (direct) tables.

  • Support for different clock domains so that engines can run at one of the following frequencies:

    • Line rate of the packet data bus used typically for engines reading or modifying packets.

    • Packet rate used for functions that occur once per packet such as an individual look-up.

    • Control rate which is the speed of the memory-mapped control interface for controlling and configuring engines.

  • Systems resulting in high performance hardware implementations, achieving up to 200 Gb/s.

  • System backpressure capability is automatically generated including the insertion of buffers providing dataflow synchronization for engines. This capability enables backpressure of the packet bus for momentarily pausing packet processing.

  • Software available for high level system simulation of the design prior to running RTL simulations.

  • AXI-Stream signaling protocol for packet interfaces.

This document describes the standard design flow beginning with the user's packet processing requirements to implementing high performance packet processing systems in a Xilinx FPGA.