The following files are generated when any of the example designs are created:
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<proj_location>/vitis_net_p4_0_ex/vitis_net_p4_0_ex.gen/sources_1/ip/vitis_net_p4_0/src/verilog/vitis_net_p4_0_pkg.sv- This file contains details in System Verilog on general configuration settings, including table structures, actions and memory map base addresses. It also includes import definitions for the DPI functions.
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<proj_location>/vitis_net_p4_0_ex/vitis_net_p4_0_ex.gen/sources_1/ip/vitis_net_p4_0/src/sw/drivers/target/src/vitis_net_p4_0_defs.c- This file contains details in C on general configuration settings, including table structures, actions and memory map base addresses.
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<proj_location>/vitis_net_p4_0_ex/vitis_net_p4_0_ex.gen/sources_1/ip/vitis_net_p4_0/src/sw/drivers/target/inc/vitis_net_p4_0_defs.h- This is the C header file.
Generally, in any project where Vitis Networking P4 is instantiated within IP Integrator, the same files are generated in the following locations:
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<project_name>/<project_name>.gen/sources_1/bd/<bd_name>/ip/<inst_name>/src/verilog/<inst_name>_pkg.sv -
<project_name>/<project_name>.gen/sources_1/bd/<bd_name>/ip/<inst_name>/src/sw/drivers/target/src/<inst_name>_defs.c -
<project_name>/<project_name>.gen/sources_1/bd/<bd_name>/ip/<inst_name>/src/sw/drivers/target/inc/<inst_name>_defs.h
Similarly, in any project where Vitis Networking P4 is instantiated within IP Catalog, the same files are generated in the following locations:
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<project_name>/<project_name>.gen/sources_1/ip/<inst_name>/src/verilog/<inst_name>_pkg.sv -
<project_name>/<project_name>.gen/sources_1/ip/<inst_name>/src/sw/drivers/target/src/<inst_name>_defs.c -
<project_name>/<project_name>.gen/sources_1/ip/<inst_name>/src/sw/drivers/target/inc/<inst_name>_defs.h