The steps to run the FiveTuple Example Design using HBM BCAM with the Questa Simulator are as follows:
- Open a Vivado project and select a device that has HBM DRAM.
- Instantiate the Vitis Networking P4 IP: Click IP Catalog and double-click Vitis Networking P4.
- Select a P4 file from the FiveTuple directory <Vivado_install_area>/data/ip/xilinx/vitis_net_p4_v1_0/example_design/examples/five_tuple.
- In the Tables tab drop-down menu under Ram Style, select High Bandwidth RAM. The Memory Resources entry should update to show the number of HBM pseudo channels used.
- Right-click vitis_net_p4_0 in the Sources window and click Open IP Example Design.
- In the new Example Design Vivado project, change the target simulator: Click Settings under PROJECT MANAGER in the panel on the left, select Simulation under Project Settings, and select the target simulator you want to use.
- Verify that the compiled library location is set correctly to point to the correct pre-compiled simulation libraries. See the Vivado Design Suite User Guide: Logic Simulation (UG900) for instructions on how to compile simulation libraries.
- Click Run Simulation under Simulation in the panel on the left. This launches the Questa simulator..
- The simulation is run for a maximum of 10 us.
Note: To run the above example design simulation
using VCS simulator, select Verilog Compiler Simulator (VCS) instead of Questa
simulator.