Advanced Calculator Example Design - 2022.2 English - UG1308

The Advanced Calculator example is based on the Calculator Example, but with two additional operations implemented with user externs: arithmetic division and square-root.

There are user extern structures defined in the generated SystemVerilog package file in Vitis Networking P4:

<proj_location>/vitis_net_p4_0_ex/vitis_net_p4_0_ex.gen/sources_1/ip/vitis_net_p4_0/src/verilog/vitis_net_p4_0_pkg.sv

These structures can facilitate the connections of the user extern I/O ports, as can be seen in

/<proj_location>/vitis_net_p4_0_ex/vitis_net_p4_0_ex/imports/example_top.sv

For example:

vitis_net_p4_0_pkg::USER_EXTERN_IN_T    user_extern_in;
vitis_net_p4_0_pkg::USER_EXTERN_VALID_T user_extern_in_valid;
vitis_net_p4_0_pkg::USER_EXTERN_OUT_T   user_extern_out; 
vitis_net_p4_0_pkg::USER_EXTERN_VALID_T user_extern_out_valid;

The different fields of the user extern I/O structures can then be accessed by name (based on the naming in calculator_extended.p4 file), as can be seen when connecting to the calc_divide_ip module:

calc_divide_ip calc_divide_ip_inst (
  .aclk (s_axis_aclk),
  .s_axis_divisor_tvalid  (user_extern_out_valid.calc_divide),
  .s_axis_divisor_tdata   (user_extern_out.calc_divide.divisor),
  .s_axis_dividend_tvalid (user_extern_out_valid.calc_divide),
  .s_axis_dividend_tdata  (user_extern_out.calc_divide.dividend),
  .m_axis_dout_tvalid     (user_extern_in_valid.calc_divide),
  .m_axis_dout_tdata      ({user_extern_in.calc_divide.quotient,
                            user_extern_in.calc_divide.remainder})
);

Alternatively, instead of using the afore-mentioned structures, parameters defined in vitis_net_p4_0_pkg.sv can be used to access the relevant bits of the user extern I/O ports, for example:

localparam USER_EXTERN_OUT_CALC_SQUARE_ROOT_WIDTH = 32; 
localparam USER_EXTERN_OUT_CALC_SQUARE_ROOT_MSB   = 95;
localparam USER_EXTERN_OUT_CALC_SQUARE_ROOT_LSB   = 64;