AXI4-Lite - 2022.2 English

Vitis Networking P4 User Guide (UG1308)

Document ID
UG1308
Version
2022.2 English
Revision

AXI4-Lite memory-mapped ports are used to control the contents of the Look-up engines and to configure, read, and write to externs. Each Vitis Networking P4 instance has a single AXI4-Lite slave interface. An AXI4-Lite crossbar is created within Vitis Networking P4 to connect all memory-mapped elements of the Vitis Networking P4 design for a given P4 program, which might include multiple tables (Direct Tables, CAMs, or HBM BCAMs) and/or multiple externs (Counters). The address map grows by 8 kB for each table/extern in the P4 program.

The address width required on the AXI4-Lite slave interface depends on the P4 program (for example, the number of tables). The address width can be found in the generated instantiation template files (<design_name>.veo/vho) or in the generated <design_name>_pkg.sv file (localparam S_AXI_ADDR_WIDTH).

Figure 1. AXI4-Lite Slave Interface and AXI4-Lite Crossbar