AXI Interfacing Tasks - 2022.2 English

Vitis Networking P4 User Guide (UG1308)

Document ID
UG1308
Version
2022.2 English
Revision

For the DPI library to be able to trigger the execution of a SystemVerilog task, the interface to the task must be known to the DPI library. In practice, this means that it must be hard-coded in both the SystemVerilog testbench and the DPI library.

For the example designs, two tasks called axi_lite_wr and axi_lite_rd are defined and can be called from the DPI library. These tasks contain the logic needed to issue writes and reads to the Vitis Networking P4 IP's AXI interface. The axi_lite_wr task takes two integer inputs (address and data), the axi_lite_rd task takes one integer input (address) and one integer output (data). You are encouraged to develop your own custom testbench. The DPI library provided with Vitis Networking P4 can be used in any such testbench, provided that the testbench defines these two tasks as described in this section.