Example Designs Using the AI Engine API - 2022.2 English

AI Engine Kernel and Graph Programming Guide (UG1079)

Document ID: UG1079
Release Date: 2022-10-19
Version: 2022.2 English

Overview
Navigating Content by Design Process
AI Engine Architecture Overview
AI Engine Memory
Tools
Single Kernel Programming
AI Engine API
Kernel Pragmas
Kernel Compiler
Kernel Simulation
Kernel Inputs and Outputs
Introduction to Scalar and Vector Programming
AI Engine API Overview
Scalar Programming
Vector Data Types
Vector Registers
Accumulator Registers
Rounding and Saturation Modes
Casting and Datatype Conversion
Vector Initialization, Load, and Store
Alignment
Initialization
Load and Store
Load and Store From Window Buffer
Load and Store Using Pointers
Load and Store Using Streams
Load and Store with Virtual Resource Annotations
Vector Arithmetic Operations
Pre-Multiplication Operations
Vector Reduction
Bit-wise Operations
Data Comparison
Data Reshaping
Iterators
Operator Overloading
Floating-Point Operations
Multiple Lanes Multiplications - sliding_mul
Matrix Multiplications - mmul
API Operation Examples
Kernel Optimization
Loops
Loop Flattening and Unrolling
Software Pipelining of Loops
Scheduling Separator
Parallel Streams Access
Restrict Keyword
Profiling Kernel Code
Using Vitis IDE and Reports
Interface Considerations
Data Movement Between AI Engines
Data Communication via Shared Memory
Data Communication via Memory and DMA
Data Communication via AXI4-Stream Interconnect
Window vs. Stream in Data Communication
Free Running AI Engine Kernel
Run-Time Parameter Specification
AI Engine and PL Kernels Data Communication
DDR Memory Access through GMIO
Example Designs Using the AI Engine API
FIR Filter
Design Analysis
Scalar Golden Reference
Vectorized Version Using a Single Kernel
Vectorized Version Using Multiple Kernels
Matrix Multiplication
Vectorized Matrix Multiplication
Data Shuffling Kernel
Introduction to Graph Programming
Prepare the Kernels
Creating a Data Flow Graph (Including Kernels)
Run-Time Ratio
Recommended Project Directory Structure
Compiling and Running the Graph from the Command Line
Window and Streaming Data API
Data Access Mechanisms
Window-Based Access
Synchronous Window Access
Window Multicasting
Synchronous Window Connection for Multi-Rate Processing
Asynchronous Window Access
Asynchronous Window Connection for Multi-Rate Processing
Stream-Based Access
Window Operations for Kernels
Window Data Types
Moving the Current Read/Write Position Forward
Moving the Current Read/Write Position Backward
Reading Data from an Input Window
Reading and Advancing an Input Window
Reading and Decrementing an Input Window
Writing Data to an Output Window
Writing and Advancing an Output Window
Stream Operations for Kernels
Stream Data Types
Reading and Advancing an Input Stream
Writing and Advancing an Output Stream
Using Streams in Parallel
Packet Stream Operations
Packet Stream Reading and Writing
Packet Processing
Run-Time Graph Control API
Graph Execution Control
Basic Iterative Graph Execution
Finite Execution of Graph
Infinite Graph Execution
Parallel Graph Execution
Timed Execution
Run-Time Parameter Specification
Specifying Run-Time Data Parameters
Run-Time Parameter Update/Read Mechanisms
Parameter Update/Read Using Graph APIs
Run-Time Graph Reconfiguration Using Control Parameters
Bypass Control Using Run-Time Parameters
Run-Time Parameter Support Summary
Specialized Graph Constructs
Look-up Tables
Static File-Scoped Tables
Global Graph-Scoped Tables
Shared Graph-Scoped Tables
FIFO Depth
Stream Switch FIFO
DMA FIFO
AI Engine Tile DMA Performance
Kernel Bypass
Explicit Packet Switching
Packet Switching Graph Constructs
Packet Switching and the AI Engine Simulator
Location Constraints
Kernel Location Constraints
Buffer Location Constraints
FIFO Location Constraints
Area Location Constraints
Hierarchical Constraints
Relative Constraints
Buffer Allocation Control
C++ Kernel Class Support
C++ Template Support
Multicast Support
AI Engine/Programmable Logic Integration
Design Flow Using RTL Programmable Logic
Design Considerations for Graphs Interacting with Programmable Logic
PL Interface Tile Capabilities
AI Engine-to-PL Rate Matching
AI Engine-PL Interface Performance
Graph Programming Model
Graph Topologies
Overview
Single Kernel Graph
Linking Multiple Sub-Graphs
Hierarchical Graphs
Recursive Graphs
Graphs with Libraries Components
Programming Model Features
Configuring input_plio/output_plio
Configuring input_gmio/output_gmio
Programming Model for AI Engine–DDR Memory Connection
Hardware Emulation and Hardware Flows
Performance Comparison Between AI Engine/PL and AI Engine/NoC Interfaces
Single Kernel Programming using Intrinsics
Intrinsics
Introduction to Scalar and Vector Programming
AI Engine Data Types
Vector Registers
Accumulator Registers
Casting and Datatype Conversion
Vector Initialization, Load, and Store
Alignment
Initialization
Load and Store
Load and Store from Vector Registers
Load and Store From Memory
Load and Store Using Pointers
Load and Store Using Streams
Load and Store with Virtual Resource Annotations
Update, Extract, and Shift
Vector Register Lane Permutations
Data Selection
Data Shuffle
Data Select
MAC Intrinsics
MAC on 32x32 bits
MAC on 32x16 bits
MAC on 16x16 bits
MAC on 8x8 bits
Options
Data Permute and MAC Examples
Loops
Floating-Point Operations
Design Analysis and Programming using Intrinsics
Matrix Vector Multiplication
Kernel Coding Bounds
Vectorization
Coding with Intrinsics
Matrix Multiplication
Kernel Coding Bounds
Vectorization
Coding with Intrinsics
Multiple Kernels Coding Example: FIR Filter
1 Gsps Implementation with Cascade Stream
Coding with Intrinsics
Adaptive Data Flow Graph Specification Reference
Return Code
Graph Objects
graph
kernel
port<T>
parameter
bypass
Graph Objects for Packet Processing
Input/Output Objects
input_gmio/output_gmio
input_plio/output_plio
Event API
Enumeration
Member Functions
Connections
Connection Constructor Templates
Port Combinations
Constraints
constraint<T>
constraint< std::vector<T>>
Mapping Constraints
Other Constraints
JSON Constraints
Node Constraints
Tile Constraint
Shim Constraint
Reserved Memory Constraint
Colocated Nodes Constraint
Non-colocated Nodes Constraint
Colocated Reserved Memories Constraint
Non-colocated Reserved Memories Constraint
Relative Constraints
Port Constraints
Buffers Constraint
Colocated Nodes Constraint
Not Colocated Nodes Constraint
Colocated Ports Constraint
Not Colocated Ports Constraint
Exclusive Colocated Ports Constraint
Colocated Reserved Memories Constraint
Not Colocated Reserved Memories Constraint
FIFO Constraint
Global Constraints
Area Group Constraint
IsomorphicGraphGroup Constraint
Using the Restrict Keyword in AI Engine Kernels
Pointer Aliasing
Strict Aliasing Rule
Restrict Keyword
Restrict Qualification
Undefined Behavior
Scope of Restrict Keyword in Inline Function
Benefits of Using the Restrict Keyword for Read/Modify/Write Loops
Derived Pointers
Summary
Non-Templated Versions of Window and Stream APIs
Window Operations for Kernels
Window Data Types
Moving the Current Read/Write Position Forward
Moving the Current Read/Write Position Backward
Reading Data from an Input Window
Reading and Advancing an Input Window
Reading and Decrementing an Input Window
Writing Data to an Output Window
Writing and Advancing an Output Window
Stream Operations for Kernels
Stream Data Types
Reading and Advancing an Input Stream
Writing and Advancing an Output Stream
Using Streams in Parallel
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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