Xil_ICacheInvalidateLine - 2022.2 English - UG643

Xilinx Standalone Library Documentation: BSP and Libraries Document Collection (UG643)
Document ID
UG643
Release Date
2022-10-19
Version
2022.2 English

Invalidate an instruction cache line.If the instruction specified by the address is cached by the instruction cache, the cacheline containing that instruction is invalidated.

Note: The bottom 4 bits are set to 0, forced by architecture.

Prototype

void Xil_ICacheInvalidateLine(INTPTR adr);

Parameters

The following table lists the Xil_ICacheInvalidateLine function arguments.

Table 1. Xil_ICacheInvalidateLine Arguments
Name Description
adr 32bit address of the instruction to be invalidated.

Returns

None.