Xil_DCacheStoreLine - 2022.2 English

Xilinx Standalone Library Documentation: BSP and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2022-10-19
Version
2022.2 English

Store a Data cache line.

If the byte specified by the address (adr) is cached by the Data cache and the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory. After the store completes, the cacheline is marked as unmodified (not dirty).

Note: The bottom 4 bits are set to 0, forced by architecture.

Prototype

void Xil_DCacheStoreLine(u32 adr);

Parameters

The following table lists the Xil_DCacheStoreLine function arguments.

Table 1. Xil_DCacheStoreLine Arguments
Name Description
adr 32bit address of the data to be stored.

Returns

None.