Xil_DCacheInvalidateLine - 2022.2 English - UG643

Xilinx Standalone Library Documentation: BSP and Libraries Document Collection (UG643)
Document ID
UG643
Release Date
2022-10-19
Version
2022.2 English

Invalidate a Data cache line.

If the byte specified by the address (adr) is cached by the data cache, the cacheline containing that byte is invalidated.If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Note: The bottom 4 bits are set to 0, forced by architecture.

Prototype

void Xil_DCacheInvalidateLine(INTPTR adr);

Parameters

The following table lists the Xil_DCacheInvalidateLine function arguments.

Table 1. Xil_DCacheInvalidateLine Arguments
Name Description
adr 32bit address of the data to be flushed.

Returns

None.