The boot code performs minimum configuration which is required for an application to run starting from processor reset state of the processor. Below is a sequence illustrating what all configuration is performed before control reaches to main function.
- Program vector table base for exception handling
- Invalidate instruction cache, data cache and TLBs
- Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, abort, system)
- Configure MMU with short descriptor translation table format and program base address of translation table
- Enable data cache, instruction cache and MMU
- Enable Floating point unit
- Transfer control to _start which clears BSS sections, initializes global timer and runs global constructor before jumping to main application
The translation_table.S contains a static page table required by MMU for cortex-A9. This translation table is flat mapped (input address = output address) with default memory attributes defined for Zynq-7000 architecture. It utilizes short descriptor translation table format with each section defining 1 MB of memory.
The overview of translation table memory attributes is described below.
Memory Range | Definition in Translation Table | |
---|---|---|
DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
Note: For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB, region after DDR and before PL is marked as undefined/reserved in translation table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 - 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size of 1 MB, it is not possible to define separate regions for them. For region 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB granual size, it is not possible to define separate region for it.