The boot code performs minimum configuration which is required for an application. Cortex-A53 starts by checking current exception level. If the current exception level is EL3 and BSP is built for EL3, it will do initialization required for application execution at EL3. Below is a sequence illustrating what all configuration is performed before control reaches to main function for EL3 execution.
- Program vector table base for exception handling
- Set reset vector table base address
- Program stack pointer for EL3
- Routing of interrupts to EL3
- Enable ECC protection
- Program generic counter frequency
- Invalidate instruction cache, data cache and TLBs
- Configure MMU registers and program base address of translation table
- Transfer control to _start which clears BSS sections and runs global constructor before jumping to main application
If the current exception level is EL1 and BSP is also built for EL1_NONSECURE it will perform initialization required for application execution at EL1 non-secure. For all other combination, the execution will go into infinite loop. Below is a sequence illustrating what all configuration is performed before control reaches to main function for EL1 execution.
- Program vector table base for exception handling
- Program stack pointer for EL1
- Invalidate instruction cache, data cache and TLBs
- Configure MMU registers and program base address of translation table
- Transfer control to _start which clears BSS sections and runs global constructor before jumping to main application
The translation_table.S contains a static page table required by MMU for cortex-A53. This translation table is flat mapped (input address = output address) with default memory attributes defined for zynq ultrascale+ architecture. It utilizes translation granual size of 4 KB with 2 MB section size for initial 4 GB memory and 1 GB section size for memory after 4 GB. The overview of translation table memory attributes is described below.
Memory Range | Definition in Translation Table | |
---|---|---|
DDR | 0x0000000000 - 0x007FFFFFFF | Normal write-back Cacheable |
PL | 0x0080000000 - 0x00BFFFFFFF | Strongly Ordered |
QSPI, lower PCIe | 0x00C0000000 - 0x00EFFFFFFF | Strongly Ordere |
Reserved | 0x00F0000000 - 0x00F7FFFFFF | Unassigned |
STM Coresight | 0x00F8000000 - 0x00F8FFFFFF | Strongly Ordered |
GIC | 0x00F9000000 - 0x00F91FFFFF | Strongly Ordered |
Reserved | 0x00F9200000 - 0x00FCFFFFFF | Unassigned |
FPS, LPS slaves | 0x00FD000000 - 0x00FFBFFFFF | Strongly Ordered |
CSU, PMU | 0x00FFC00000 - 0x00FFDFFFFF | Strongly Ordered |
TCM, OCM | 0x00FFE00000 - 0x00FFFFFFFF | Normal inner write-back cacheable |
Reserved | 0x0100000000 - 0x03FFFFFFFF | Unassigned |
PL, PCIe | 0x0400000000 - 0x07FFFFFFFF | Strongly Ordered |
DDR | 0x0800000000 - 0x0FFFFFFFFF | Normal inner write-back cacheable |
PL, PCIe | 0x1000000000 - 0xBFFFFFFFFF | Strongly Ordered |
Reserved | 0xC000000000 - 0xFFFFFFFFFF | Unassigned |