As SHA-384 and SHA-512/t is simply truncated SHA-512 with different initialization values, they share the same internal structure, as illustrated in the figure above.
A single instance of one of SHA-384/SHA-512/SHA512-224/SHA512-256 processes input message at the rate of
1024 bit / 84 cycles at 313.28MHz/323.31MHz/310.26MHz/313.57MHz.
The hardware resource utilizations of SHA-384 is listed in Table 160 below:
| BRAM | DSP | FF | LUT | CLB | SRL | clock period(ns) |
| 0 | 0 | 15494 | 8317 | 2045 | 0 | 3.192 |
The hardware resource utilizations of SHA-512 is listed in Table 161 below:
| BRAM | DSP | FF | LUT | CLB | SRL | clock period(ns) |
| 0 | 0 | 15497 | 8318 | 2015 | 0 | 3.093 |
The hardware resource utilizations of SHA-512/224 is listed in Table 162 below:
| BRAM | DSP | FF | LUT | CLB | SRL | clock period(ns) |
| 0 | 0 | 15498 | 8318 | 2101 | 0 | 3.223 |
The hardware resource utilizations of SHA-512/256 is listed in Table 163 below:
| BRAM | DSP | FF | LUT | CLB | SRL | clock period(ns) |
| 0 | 0 | 15497 | 8322 | 2029 | 0 | 3.189 |