Step 2: Infer clock, reset, AXI interfaces and associate them with clock - 2022.2 English - XD099

Here we first use ipx::infer_bus_interface command to infer ap_clk and ap_rst_n as AXI bus signals. Generally if ap_clk is the only clock we used in the RTL kernel, this command can be omitted. If we use more clocks (ap_clk_2, ap_clk_3, …) in the design, we must use the ipx::infer_bus_interface command to infer the ports explicitly.

ipx::infer_bus_interface ap_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface ap_rst_n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]

All AXI interfaces will be inferred automatically. In this design, these AXI ports include: a control AXI slave port s_axi_control, four AXIS slave ports axis_slv0 ~ 3 and four AXIS master ports axis_mst0 ~ 3.

Then we use ipx::associate_bus_interfaces command to associate the automatically inferred AXI interfaces and reset signal to ap_clk.

ipx::associate_bus_interfaces -busif s_axi_control  -clock ap_clk [ipx::current_core]
ipx::associate_bus_interfaces -busif axis_mst0      -clock ap_clk [ipx::current_core]
  ...
ipx::associate_bus_interfaces -busif axis_slv0      -clock ap_clk [ipx::current_core]
  ...
ipx::associate_bus_interfaces -clock ap_clk -reset ap_rst_n [ipx::current_core]