Step 1: Create Vivado project and add design sources - 2022.2 English - XD099

Firstly we need to create a Vivado project containing the source files. The script use the Tcl command create_project, add_files and update_compiler_order to finish this step. All RTL source codes, generated IP file (xci file) and XDC file should be added into the newly created project.

Finally the ipx::package_project Tcl command is used to initialize the IP packaging process.

create_project krnl_aes ./krnl_aes
add_files -norecurse {
        ../rtl/aes_wrapper.sv ... ...              \
        ../ip_generation/clk_gen/clk_gen.xci      \
        ../ip_generation/axi_clock_converter/axi_clock_converter.xci \
        ../ip_generation/axis_clock_converter/axis_clock_converter.xci \
        ../krnl_aes.xdc                     \
       }
update_compile_order -fileset sources_1
ipx::package_project -root_dir ./krnl_aes_ip -vendor xilinx.com -library user -taxonomy /UserIP -import_files -set_current true

In this step, you may see a warning information like: WARNING: [IP_Flow 19-5101] Packaging a component with a SystemVerilog top file is not fully supported. Please refer to UG1118 ‘Creating and Packaging Custom IP’. Currently the Vitis tool chain requires the port definition of the top module be traditional Verilog style. Though the top level module krnl_aes.sv uses some SystemVerilog syntax (SystemVerilog interface objects), but it uses the traditional Verilog style port definition, so you could omit this warning.