Get Moving with Alveo - 2022.2 English - XD099

Introduction

Version: Vitis 2022.2

Xilinx FPGAs and Versal ACAP devices are uniquely suitable for low-latency acceleration of high performance algorithms and workloads. With the demise of traditional Moore’s Law scaling, design-specific architectures(DSAs) are becoming the tool of choice for developers needing the optimal balance of capability, power, latency, and flexibility. But, approaching FPGA and ACAP development from a purely software background can seem daunting.

With this set of documentation and tutorials, our goal is to provide you with an easy-to-follow, guided introduction to accelerating applications with Xilinx technology. We will begin from the first principles of acceleration: understanding the fundamental architectural approaches, identifying suitable code for acceleration, and interacting with the software APIs for managing memory and interacting with the target device in an optimal way.

This set of documents is intended for use by software developers, it is not a low-level hardware developer’s guide. The topics of RTL coding, low-level FPGA architecture, high-level synthesis optimization, and so on are covered elsewhere in other Xilinx documents. Our goal here is to get you up and running with Vitis quickly, with the confidence to approach your own acceleration goals and grow your familiarity and skill with Xilinx over time.

Provided Design Files

In this directory tree you will find a collection of documents and a directory named design_source. The design_source directory contains all of the design elements - hardware and software - for the tutorial you’re currently reading. The example applications correspond to specific sections in the guide. Every effort has been made to keep the code samples as concise and “to the point” as possible.

Build the Software and Hardware

Attached Makefile can be used to build the design:

The above Makefile flow would need PLATFORM and PLATFORM_REPO_PATH

export PLATFORM=xilinx_u250_gen3x16_xdma_4_1_202210_1 # Example to set the PLATFORM before launching the run 
export PLATFORM_REPO_PATH=/opt/xilinx/platforms/      # Example to set the PLATFORM_REPO_PATH before launching the run

This tutorial uses OpenCV for the application, please set the OpenCV env variable as below

export OPENCV_INCLUDE=<path>/opencv-4.4.0/include
export OPENCV_LIB=<path>/opencv-4.4.0/lib
export LD_LIBRARY_PATH=<path>/opencv-4.4.0/lib:$LD_LIBRARY_PATH

Once the build is complited, a folder build under directory design_source will contain all the executables and alveo_example.xclbin to run the tutorial

Note: The hw_emu is not tested for this release.