The Hardware Acceleration Design Tutorials illustrate higher-level concepts or design flows, walk through specific examples or reference designs, and more complex and complete designs or applications.
The landing page of Hardware Acceleration contains important information including tool version, environment settings, and a table describing the platform, kernels, and supported features or flows of each tutorial. It is strongly recommended that you review the details before starting to use the acceleration tutorials.
Tutorial |
Description |
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This tutorial walks through the process of analyzing and optimizing a 2D convolution used for real-time processing of a video stream. |
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This tutorial shows how to achieve a 10x speed-up on a data analytics application using a combination of kernel and host code optimization techniques. |
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This tutorial demonstrates how to integrate free-running RTL kernels, Vitis Library functions, and custom Vitis HLS kernels into a real system. |
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This tutorial demonstrates the full flow to implement a HLS kernel from algorithm model to hardware. |
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This tutorial demonstrates how to develope a complex RTL kernel from scratch via batch mode without GUI environment. |
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This tutorial puts in practice the concepts of FPGA acceleration and illustrates how to gradually optimize a hardware accelerator implementing the Cholesky matrix decomposition algorithm. |
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This tutorial demonstrates how to optimize your CPU host code to get the most out of interaction between your hardware accelerators and your runtime software. |
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This tutorial demonstrates how to integrate Aurora IP in user design on Alveo card with Vitis flow to realize high-speed inter-card communications. |
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This tutorial demonstrates how to design an application of finding shortest path with Vitis Graph library on Alveo U50. |
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This tutorial provides you with an easy-to-follow, guided introduction to accelerating applications with Xilinx technology, understanding the fundamental architectural approaches, identifying suitable code for acceleration, and interacting with the software APIs for managing memory and interacting with the target device in an optimal way. |