Create the Vitis Project - 2022.2 English

1. To open the Vitis IDE, enter vitis in the command line.

2. Select ./mixing-c-rtl-kernels/workspace as the workspace directory, and click Launch.

3. From the Welcome screen select Create Application Project to open the New Project wizard.

4. The first page displays a summary of the process. Click Next to proceed.

5. From the Platform page select the xilinx_u200_gen3x16_xdma_2_202110_1 platform and click Next.

6. From the Application Project Details page, name your project rtl_project and click Next.

7. Under SW Acceleration Templates, select Empty Application, and click Finish. This creates a Vitis IDE project.

Next, generate an RTL-based kernel from within the Vitis IDE.

1. Select the menu command Xilinx > Launch RTL Kernel Wizard > rtl_project_kernels. This opens the RTL Kernel Wizard Welcome page.

2. The first page is a summary of the process. Review it and click Next.

3. In the General Settings dialog box, keep all the default settings, and click Next.

4. In the Scalars dialog box, set the number of scalar arguments to 0, and click Next.

5. In the Global Memory dialog box, keep all the default settings, and click Next.

6. In the Streaming Interfaces dialog box, keep all the default settings, and click Next.
   The Summary dialog box is displayed and provides a summary of the RTL kernel settings and includes a function prototype which conveys what a kernel call would look like as a C function.

7. Click OK.

The RTL Kernel source files have now been created.