Controlling Vivado Synthesis and Implementation through the Vitis Compiler - 2022.2 English - XD099

NOTE: In this tutorial, run all instructions from the reference-files/run directory.

The –-vivado switch is paired with properties or parameters to configure the Vivado tools. For instance, the --vivado switch can configure optimization, placement, and timing, or set up emulation and compile options. In the command line flow, properties are specified as --vivado.prop <object_type>.<object_name>.<prop_name> where:

• prop: Required keyword that signifies the specified property.

• object_type: Defines the first class object type to assign the property to.

• object_name: Specifies the object instance to attach to.

• prop_name: Defines the property_name/value pair which defines both the name and the value to assign.

While you can use --vivado options from the v++ command line, it makes more sense to do some from configuration files specified by the --config option. This is explained in Vitis Compiler Configuration File in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416). In this tutorial, you will use the following options as examples to see how to control Vivado synthesis and implementation:

• Completely flatten the hierarchy during RTL synthesis by specifying the FLATTEN_HIERARCHY=full property.

  • --vivado.prop run.my_rm_synth_1.{STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY}={full}

• Use the NoTimingRelaxation directive during the Vivado routing step by using the STEPS.ROUTE_DESIGN property.

  • --vivado.prop run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE}={NoTimingRelaxation}

In this tutorial, the -–vivado command options are defined in the design.cfg file, which will be used during the hardware build process.

TIP: Because it is running Vivado synthesis and implementation, the hardware build process (t=hw) can take a significant amount of time to run.

1. Compile the kernel with the Vitis compiler and link it with the platform file to produce the device binary (.xclbin) using the following commands.

   v++ -t hw --config design.cfg -c -k apply_watermark -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo ../src/krnl_watermarking.cl
   v++ -t hw -s --config design.cfg -R2 -l -o apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xclbin apply_watermark.hw.xilinx_u200_gen3x16_xdma_2_202110_1.xo
   

2. Open the design.cfg file and get familiar with different options. The following list describes some of the command options.

   Command Options Descriptions

   • -t hw: Build target is hardware

   • platform=xilinx_u200_gen3x16_xdma_2_202110_1: Specify the xilinx_u200 platform

   • debug=1: Generate debug info

   • --hls.pre_tcl max_memory.tcl: Specifies a Tcl script to configure the interface to generate a separate AXI4 interface for each port

   • -c: Compile the kernel

   • -k apply_watermark: Name the kernel

   • ../src/krnl_watermarking.cl: Specify source files

   • sp=apply_watermark_1.m_axi_gmem0:DDR[0]: Specify DDR bank connection

   • --config design.cfg: Set the Vivado Synthesis and Implementation options

   • -R2: Set Report Level to 2 to generate DCPs for each implementation step

   • -l: Link the kernel

   • nk=apply_watermark:1:apply_watermark_1: Specify kernel instance number and name

3. To check that the Vivado synthesis and implementation options are applied, open _x/logs/link/vivado.log, and search for flatten_hierarchy and NoTimingRelaxation. You will find following lines indicating that the options have taken effect:

   • Command: synth_design -top pfm_dynamic -part xcu200-fsgd2104-2-e -flatten_hierarchy full -mode out_of_context

   • Command: route_design -directive NoTimingRelaxation

You have successfully applied properties to manage or influence the results of synthesis and implementation in the Vivado Design Suite.