System Timing Failure - 2022.1 English

Vitis Guidance Messaging (UG1315)

Document ID
Release Date
2022.1 English


One or more timing paths in the system failed timing requirements. The intended frequency cannot be achieved and the auto frequency scaling mechanism reduced the system clock frequency to enable proper functionality.


The current implementation cannot operate on the desired target frequency. The frequency of the system clock was automatically reduced to achieve correct functionality. While this ensures correct functionality, this might not satisfy the overall implementation goal. To achieve the overall system performance (implementation goal), the user will have to investigate timing paths and determine the root cause for the problematic paths.


Issues identified as system timing violations are best debugged through the Vivado® Design Suite. Especially when a system is assembled from many kernels or one large kernel utilizing almost all resources, the implementation might not be able to achieve the target frequency due to place and route delays not accounted for by the individual system components. In this case, target requirements might be achieved by scheduling critical sections with even higher target frequency to allow extra room for delays introduced during place and route.