System Clock Maximum Frequency - 2022.1 English

Vitis Guidance Messaging (UG1315)

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2022.1 English


Automatic frequency scaling failed because the system clock has an original frequency exceeds the maximum frequency supported by the run time.


The current system implementation is capable of operating at a higher frequency than the maximum frequency supported by the run time. The compiler will not select a frequency higher than the run time maximum.

If all design parameters are satisfied with this implementation, no further action is required. However, if the design requires too much area on the FPGA, it might be beneficial to change the system implementation and trade-off maximum implementation speed with resource requirements.


This design has too much positive slack, which implies that more operations can potentially be scheduled in one cycle without impacting the target clock frequency. Try reducing the target frequency or reducing clock uncertainty while compiling.