Step 4: Customizing IP - 2022.1 English - UG995

Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995)
Document ID
UG995
Release Date
2022-04-26
Version
2022.1 English
  1. Double-click the AXI Interconnect core to open the Re-Customize IP dialog box, as shown in the following figure:

  2. From the Top Level Settings Tab, for the Number of Master Interfaces field, select 5 from the drop down menu.
  3. Leave all the remaining options set to their default values, and click OK.

    The Vivado IP integrator re-customizes the AXI Interconnect, changing the number of master interfaces to five, and adding the necessary clock and reset pins to support these new master interfaces, as shown in the following figure:



  4. Connect all the new clocks to the ACLK port, and the new resets to the ARESETN port.

    Now you can connect the five slave IP cores to the AXI Interconnect.

  5. Connect the S_AXI interface of the AXI BRAM Controller to M00_AXIinterface of the AXI Interconnect.
  6. Connect the s_axi_aclk and the s_axi_aresetn pins of the AXI BRAM Controller to the ACLK and ARESETN ports. The following figure shows these connections.

  7. Using the same steps, connect the remaining slave IP cores in the design to the AXI Interconnect.
    Tip: The order of connections between the S_AXI interface pins on the IP slaves and the M_AXI interface pins on the AXI Interconnect does not matter.
  8. Click Regenerate Layout on the menu at the top of the banner.

    The IP integrator design canvas should look similar to what shows in the figure below.



    At this point, you should save the IP integrator subsystem design.

  9. Click the File > Save Block Design command from the main menu.