Step 8: Implementing the Design - 2022.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

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2022.1 English
  1. In the Flow Navigator, select Run Implementation to run place and route on all configurations.

    This action runs implementation first for impl_1 and then for child_0_impl_1. In addition to running place and route for the two runs with all the DFX requirements in place, it does a few more tasks specific to DFX. After impl_1 completes, Vivado automatically:

    • Writes a module-level (OOC) checkpoint for the routed multiplier RM.
    • Carves out the logic in the RP to create a static-only design image. This is done by calling update_design -black_box for the RP instance.
    • Locks all placement and routing for this static-only design. This is done by calling lock_design -level routing.
    • Saves this locked static parent image to be reused for all child runs.

    In addition, when the child run completes, a module-level checkpoint is created for the routed adder RM. A locked static design image would be identical to the parent, so this step is not necessary.

    In Vivado projects, dependency management is handled by the Vivado IDE. If sources are modified, any applicable runs will be marked out-of-date. The parent-child relationship means these checks must understand dependencies. For example, if add.v is modified, only its OOC synthesis run and the child implementation run would be marked out of date.

    If only specific configuration runs are desired, these can be individually selected within the Design Runs window. Note that a parent run must be completed successfully before a child run can be launched, as the child run starts by importing the locked static design from the parent.

    Figure 1. Both Configurations Routed

  2. When the implementation runs complete, select Open Implemented Design and then OK in the resulting pop-up dialog.
    Figure 2. Open the impl_1 Configuration
    Even though the design has been processed through to the child implementation run, selecting Open Implemented Design opens the parent run by default. Use the pulldown selection to choose the desired implementation run.
    Figure 3. Device View of the Routed Parent Design

    This is the routed design for the multiplier configuration. Next, take a look at the frameset of the placement and routing areas.

  3. In the Tcl Console, cd to the current project directory (if you are not already there). Then run these commands to source visualization scripts:
    source project_1.runs/impl_1/hd_visual/pblock_my_math_Routing_AllTiles.tcl
    highlight_objects -color yellow [get_selected_objects]

    This first Tcl script identifies the frames that are valid for routing the reconfigurable part of the design. Note that it extends to the height of the clock region(s) occupied by the Pblock, and extends left and right by two programmable units. (Programmable units are pairs of resource columns.)

  4. Run these commands to identify the frameset used for placing the reconfigurable part of the design.
    source project_1.runs/impl_1/hd_visual/pblock_my_math_Placement_AllTiles.tcl
    highlight_objects -color blue [get_selected_objects]

    This highlighted region will be either the Pblock area itself, or an area just smaller than the Pblock if the Pblock did not align with programmable units boundaries.

    Your device view should look something like this:

    Figure 4. The math RP Highlighted Showing Placement (Blue) and Routing (Yellow) Boundaries

    Static logic may be placed in the expanded routing region, which is now the remaining yellow region. Static routing can use any resources in the device.

  5. In the Flow Navigator, select Report Timing Summary and click OK to analyze the design timing.
  6. In the Timing tab, select the Design Timing Summary and click on the value for the Worst Negative Slack (WNS) to bring up the top ten worst paths. Double-click on the first path to open the timing summary on that path.

    In this timing report, note that in the Clock Paths and the Data Path, there is a new column labeled Partition that shows which partition (or boundary) that particular part of the path is in.

    You might need to toggle the visibility of the Partition column by right-clicking on the table header and checking Partition. Then expand the timing report window or adjust the column widths to see the Partition column, the last column on the right.
    Figure 5. Timing Report Path with Partitions Shown

  7. Close the impl_1 implemented design with File > Close Implemented Design.