Step 7: Modifying the DFX Controller in the FPGA - 2022.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2022-05-31
Version
2022.1 English

In the final step, you add a new Reconfigurable Module to the Shifter VSM. In the create_prom.tcl script, you can see that two black box modules have already been generated. These represent two new RMs that may have been created after the static design was deployed to the field. You modify the DFX Controller settings to access one of these RMs by assigning the size, address, properties and trigger conditions.

  1. Shut down the Shift VSM so it can be modified.
    dfxc_shutdown_vsm vs_shift
  2. Check the status of the first three RM IDs to see their register bank assignments.
    dfxc_show_rm_configuration vs_shift 0
    dfxc_show_rm_configuration vs_shift 1
    dfxc_show_rm_configuration vs_shift 2

    Currently, RM ID 2 is not assigned to any partial bitstreams. This is the behavior as requested when the initial trigger mapping was done during core customization.

  3. When the MCS file is created for the prom, it adds additional blanking RMs that are already loaded into the BPI flash. Use this sequence of commands to reassign the trigger mapping for slot 2 to point to the blanking Reconfigurable Module for vs_shift.
    dfxc_write_register vs_shift_rm_control2 0

    This defines the settings for the RM_CONTROL register for slot 2. No shutdown, startup, or reset are required. Note how for the other two slots, the differing reset durations lead to different control values.

    dfxc_write_register vs_shift_rm_bs_index2 327684

    This assigns a new bitstream reference for this RM ID.

    dfxc_write_register vs_shift_trigger2 2

    This assigns the trigger mapping such that trigger index 2 retrieves RM 2. The RM_BS_INDEX register within the DFX Controller is 32 bits but is broken into two fields. UltraScale devices require clearing and partial bitstreams. These bitstreams are identified separately with unique IDs, but referenced together in this field.

    This value of 327684 converts to 0000000000000101_0000000000000100 in binary. Or more simply, ID 5 for the upper 16 bits for the CLEAR_BS_INDEX and ID 4 for the lower 16 bits for the BS_INDEX. This assignment sets the clearing and partial bitstream identifiers at the same time.

    dfxc_show_rm_configuration vs_shift 2

    This shows the current state of RM ID 2. Note the changes from the prior call to this command.

  4. Complete the RM ID 2 customization by setting the bitstream details.
    dfxc_write_register vs_shift_bs_size4 375996
    dfxc_write_register vs_shift_bs_address4 12935168
    dfxc_write_register vs_shift_bs_size5 26036
    dfxc_write_register vs_shift_bs_address5 13312000
  5. Restart the VSM and then issue trigger events to it using software, as there is no pushbutton assigned for slot 2.
    dfxc_restart_vsm_no_status vs_shift
    dfxc_send_sw_trigger vs_shift 2

    Switch between values of 0,1, and 2 to reload different partial bitstreams. The blanking bitstream in slot 2 removes the shifter function, so no activity on the LEDs is seen.

    Note that this same sequence of events could not be performed for the Count VSM as it is currently configured, even knowing that the PROM image has a Count black box partial bitstream sitting at address 13338624 with a size of 274104. During DFX Controller customization, this VSM was selected to have only 2 RMs allocated, so expansion is not permitted.