Step 5: Add a New Reconfigurable Module - 2022.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

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2022.1 English

Dynamic Function eXchange would not be very compelling without multiple Reconfigurable Modules (RM) to swap between, so the next step is to create a new RM for the RP that now exists. Follow the instructions below or source create_rp1rm2.tcl to automate the steps.

  1. Right-click on the rp1 instance and select Create Reconfigurable Module. In the dialog box that opens, give the RM a name of rp1rm2 and click OK.

    A new block design is created and opened. The diagram consists of three input pins, which are the same port list as the first RM for the rp1 partition. The port list for each RM for a given RP must be identical, even if not all of the ports are used by each RM. Note that in the log (and script) the create_bd_design command uses the -boundary_from_container option, copying the explicit port list from the block design container.

  2. Add a new IP to the canvas by clicking the + icon and using the search field to find the AXI GPIO IP. Add it to the canvas, then double-click to customize. Check the All Inputs box for GPIO, ensure the GPIO Width is set to 32, then OK to return to the canvas.
    Figure 1. Customize the GPIO IP for RM2
  3. Click the + again and use the search field to add a Constant IP to the canvas. Double-click to customize. Change the Const Width to 32 and Const Val to 0xFACEFEED. Click OK to accept the edits.
    Figure 2. Customize the Constant IP for RM2
  4. Connect the pins to create the diagram as shown in following figure.
    Note: You will need to expand the GPIO port to expose the 32-bit input bus to match the type of the Constant dout bus. Regenerate the layout to make it look nice.
    Figure 3. Completed RM2 Block Design
  5. Change to the Address Editor tab and note that no addresses have been assigned. Right-click on the row for /axi_gpio_0/S_AXI and select Assign. This sets a 64K range starting at address 0x4000_0000.
  6. Modify the Master Base Address so it starts at 0xA001_0000 then keep the Range at 64K.
    Figure 4. Final Assignment of the Address Range for the GPIO
  7. Validate and save the rp1rm2 block design.

    In this simple design, there are only two differences between rp1rm1 and rp1rm2:

    1. The S_AXI base addresses are different.
    2. The constant values that can be read via GPIO are different.

    This first difference will be used to show that device tree overlays must be created and managed for designs that may have different requirements between Reconfigurable Modules. The second difference will be used to confirm that dynamic reconfiguration in hardware has been done successfully.