RTL Project flow in the Vivado IDE - 2022.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID: UG909
Release Date: 2022-06-07
Version: 2022.1 English

Introduction
Navigating Content by Design Process
Introduction to Dynamic Function eXchange
Terminology
Design Considerations
Design Requirements and Guidelines
Design Performance
Design Criteria
Dynamic Function eXchange Licensing
Common Applications
Networked Multiport Interface
Configuration by Means of Standard Bus Interface
Dynamically Reconfigurable Packet Processor
Asymmetric Key Encryption
Summary
Vivado Software Flow
Dynamic Function eXchange Commands
Synthesis
Synthesizing the Top Level
Synthesizing Reconfigurable Modules
Reading Design Modules
Method 1: Add and Link Files
Method 2: Read Netlist Design
Method 3: Open/Read Checkpoint
Method 4: Open Checkpoint/Update Design
Adding Reconfigurable Modules with Sub-Module Netlists
Reading Design Constraints
Implementation
Preserving Implementation Data
Dynamic Function eXchange Constraints and Properties
Define a Module as Reconfigurable
Create a Floorplan for the Reconfigurable Region
Floorplan in the Vivado IDE
Manage the Reconfigurable Partition Floorplan
Programmable Units
Using Visualization Scripts
Timing Constraints
Partition Pins
Apply Reset After Reconfiguration
Software Flow
Synthesis
Implementation
Incremental Compile
Reporting
Verifying Configurations
Bitstream Generation
Tcl Scripts
Nested Dynamic Function eXchange
Nested DFX Structure and Commands
Design Structure
Tcl Commands to Manage Nested DFX
Implementation Design Flow
Create Reconfigurable Module Results Under A1
Create Reconfigurable Module Results Under A2
Checking Current Status
Static Design Updates
Verification Passes
Bitstream Creation
Nested DFX Design Considerations
Floorplanning
Decoupling
Dynamic Function eXchange Controller IP
Bitstream Version and Usage Compatibility
Supported/Unsupported Features
Abstract Shell for Dynamic Function eXchange
Abstract Shell Design Flow
Implementing Reconfigurable Modules in Abstract Shells
Generating Partial Bitstreams
Generating Partial Bitstreams from Full Configurations
Generating Partial Bitstreams from Abstract Shells
Device Programming Strategies
Additional Solution Details
Logical Connectivity Contents
Proprietary Design Information and Licensed IP
Abstract Shell and Nested DFX
Design Considerations
False Paths inferred during Abstract Shell Creation
Supported/Unsupported Features
Supported Features
Unsupported Features
Known Issues and Limitations
Vivado Project Flow
RTL Project flow in the Vivado IDE
Flow Summary
Tcl Commands
Steps for Creating and Using a Dynamic Function eXchange Project
Creating a Dynamic Function eXchange Project
Defining Reconfigurable Partitions
Completing the Dynamic Function eXchange Project Structure
Editing Reconfigurable Modules
Editing Configurations
Editing Configuration Runs
Adding or Modifying Reconfigurable Modules or Configurations
Adding Reconfigurable Module Constraints
Adding or Creating IP Sources
Implementing the DFX Design
Generating Bitstreams
Supported/Unsupported Features
IP Integrator Using Block Design Containers
Top-Down Flow
Bottom-Up Flow
Turn a Block Design Container into a Reconfigurable Partition
Removing a Block Design Container
Add New Design Sources to the Block Design Container
Update Port Boundaries within a BDC
Address Apertures
Prepare the Design for Implementation
Running the Dynamic Function eXchange Wizard
Editing Configurations
Editing Configuration Runs
Supported/Unsupported Features
Design Considerations and Guidelines for All Xilinx Devices
Dynamic Function eXchange IP
Design Hierarchy
Dynamic Reconfiguration Using the DRP
Packing Logic
Design Instance Hierarchy
Reconfigurable Partition Interfaces
Partition Pin Placement
Active-Low Resets and Clock Enables
Decoupling Functionality
Black Boxes
Effective Approaches for Implementation
Building Up Implementation Requirements
Configuration Analysis Report
Complexity
Clocking
Timing
Summary
Managing Constraints for a DFX Design
Constraint Creation
Constraint Application
Defining Reconfigurable Partition Boundaries
Avoiding Deadlock
Design Revision Checks
Simulation and Verification
Design Considerations and Guidelines for 7 Series and Zynq Devices
Design Elements Inside Reconfigurable Modules
Global Clocking Rules
Creating Pblocks for 7 Series Devices
Automatic Adjustments for Reconfigurable Partition Pblocks
Creating Reconfigurable Partition Pblocks Manually
Using High Speed Transceivers
Dynamic Function eXchange Design Checklist (7 Series)
Design Considerations and Guidelines for UltraScale and UltraScale+ Devices
Design Elements Inside Reconfigurable Modules
Creating Pblocks for UltraScale and UltraScale+ Devices
Automatic Adjustments for PU on Pblocks
Sharing Configuration Frames between RP and Static Logic
Expansion of CONTAIN_ROUTING Area
UltraRAM Behavior
Floorplanning Rules for Clocks Inside an RP
Global Clocking Rules
I/O Rules
Using High Speed Transceivers
Dynamic Function eXchange Checklist for UltraScale and UltraScale+ Device Designs
Recommended Floorplanning Constraints
Reduce the Number of Partition Pins
Recommended Netlist Structure at the DFX Boundary for Maximum PPLOC Reduction
Avoid RP to RP Direct Paths
Avoid Multiple RPs Driving Same Static Leaf Cell
Replicate Static Register Driving Multiple RPs
Register Inputs and Outputs of RMs
Reduce Bleed Over of Static Nets to the Reconfigurable Pblocks
Make Pblocks as Rectangular as Possible to Avoid Unroutability at the Edges
Considerations for Static Pblocks with CONTAIN_ROUTING Enabled
Keep Routability as a Factor in Utilization
Reduce the Number of Unique Control Sets
Reduce the Detour Due to Hold Violations
Exclude Containment Requirement for Nets
Avoid Disjointed Pblocks for Better Routability and Timing Closure
Design Considerations and Guidelines for Versal Devices
Design Elements Inside Reconfigurable Modules
Creating Pblocks for Versal Devices
Sharing Clock Region between Multiple Reconfigurable Pblocks
HD_Visual Scripts
BLI Floorplan Alignment
Expanded Routing
Clocking Resources
Global Clocking Rules
Major Enhancements for Clocking in Versal DFX Compared to UltraScale+
Known Restrictions for Clocking in Versal DFX
Network on Chip
NoC Completely in Static
NoC Paths Shared between RP and Static
RP to RP NoC Communication With a Static Endpoint NoC
NoC Completely in an RP
NoC DFX DRCs in IP Integrator: Problems and Solutions
Hardened DDR Memory Controllers
Logical Decoupling
Debugging Versal DFX Designs
Versal Use Cases
Recommended Floorplanning Constraints
Configuring the Device
Configuration Modes
Bitstream Type Definitions
Full Configuration Bitstreams
Partial Bitstreams
Blanking Bitstreams
Clearing Bitstreams
Dynamic Function eXchange through ICAP for Zynq Devices
Tandem Configuration and Dynamic Function eXchange
Formatting BIN Files for Delivery to Internal Configuration Ports
Summary of BIT Files for UltraScale Devices
System Design for Configuring an FPGA
Partial BIT File Integrity
Configuration Frames
Configuration Time
Configuration Debugging
Using Vivado Debug Cores
Configuration Solutions for Versal Devices
Partial PDI Creation and Details
Supported Boot Modes and Performance
Programming Image Compression
NoC Clock Gating Issue
Known Issues and Limitations
Known Issues
Known Limitations
Hierarchical Design Flows
List of Supported Devices
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

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