Design Considerations - 2022.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2022-06-07
Version
2022.1 English

The flow to create the initial configuration of the design, establishing the static design results, is no different for Abstract Shell than the standard DFX flow. However, watch closely for an Abstract Shell when two RPs connect to each other. If there is no synchronous element on a path between two RPs, you can never be certain any possible RM combination in the two RPs is able to meet timing. While this is technically legal in DFX, Xilinx strongly recommends avoiding this scenario.

Two similar Design Rule Checks alert you to this scenario:

  1. HDPR-34 – Signal '<object(s)>' is a direct path that connects RP '<object(s)>' and '<object(s)>' without a synchronous timing point in the static design. This omission might lead to timing failures in hardware depending on the RMs that are currently loaded. To close timing on all possible synchronous paths, ensure that any possible path contains at most a segment in only a single RP.
  2. HDPR-35 – A path connects an RP '<object(s)>' and '<object(s)>' without a synchronous timing point in the static design. This omission might lead to timing failures in hardware depending on the RMs currently loaded. To close timing on all possible synchronous paths, ensure that any possible path contains at most a segment in only a single RP. The following is a list of nets (up to the first 15) in the path: <name>.

Run all DFX DRCs on the initial configuration of the design before creating Abstract Shells. If you encounter these particular alerts, please modify your static design accordingly.