VHDL Entity Declarations - VHDL Entity Declarations - 2022.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID
UG901
Release_Date
2022-06-06
Version
2022.1 English

The I/O ports of the circuit are declared in the entity. Each port has a:

•name

•mode (in, out, inout, buffer)

•type