Vivado synthesis recognizes Flip-Flops, Registers with the following control signals:
•Rising or falling-edge clocks
•Asynchronous Set/Reset
•Synchronous Set/Reset
•Clock Enable
Flip-Flops, Registers and Latches are described with:
•sequential process (VHDL)
•always block (Verilog)
•always_ff for flip-flops, always_latch for Latches (SystemVerilog)
The process or always block sensitivity list should list:
•The clock signal
•All asynchronous control signals