ASYNC_REG Verilog Example - ASYNC_REG Verilog Example - 2022.1 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document_ID
UG901
Release_Date
2022-06-06
Version
2022.1 English
(* ASYNC_REG = "TRUE" *) reg [2:0] sync_regs;