Running Methodology Checks - 2022.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

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2022.1 English

The Vivado Design Suite provides automated methodology checks based on the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949) using the Report Methodology command.

You can generate a methodology report on an opened, elaborated, synthesized, or implemented design. For an elaborated design, the methodology report checks the XDC and RTL files. For information on running the methodology report using Tcl commands, see this link command in the Vivado Design Suite Tcl Command Reference Guide (UG835).