Summary - Summary - 2022.1 English - UG1393

As discussed in earlier topics, several important aspects of coding the kernel for FPGA acceleration using C/C++ include the following points:

1. Consider using arbitrary precision data types, ap_int, and ap_fixed.
2. Understand kernel interfaces to determine scalar and memory interfaces. Use bundle switch with different names if separate DDR memory banks will be specified in the linking stage.
3. Use Burst read and write coding style from and to the memory interface.
4. Consider exploiting the full width of DDR banks during the data transfer when selecting width of memory data inputs and outputs.
5. Get the greatest performance boost using pipelining and dataflow.
6. Write perfect or semi-perfect nested loop structure so that the v++ compiler can flatten and apply pipeline effectively.
7. Unroll loops with a small number of iterations and low operation count inside the loop body.
8. Consider understanding the array access pattern and apply complete partition to specific dimensions or apply block or cyclic partitioning instead of a complete partition of the whole array.
9. Minimize the array access by using local cache to improve kernel performance.
10. Consider inlining the function, specifically inside the pipelined region. Functions inside the dataflow should not be inlined.
11. Consider using auto-restarting kernels for data-driven designs with streaming data from the I/O pins (Ethernet, SerDes) of the device, or from another kernel.