Revision History - Revision History - 2022.1 English - UG1387

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2022-05-25
Version
2022.1 English

The following table shows the revision history for this document.

Section Revision Summary
05/25/2022 Version 2022.1
Design Flow Diagrams Added new section.
Platform-Based Design Flow Best Practices Added table.
Design Planning Considerations for DFX based Vitis Acceleration Platform Development Added new section.
Design Planning Considerations for Classic SoC Boot Added new section.
Design Planning Considerations for Tandem Configuration Added new section.
Defining a Good Block Design Hierarchy Added new section.
Instantiating Block Designs Added benefits of each approach.
Using Different Source Files in IP Integrator Added design hierarchy diagrams for each section.
Recommendations for Designing with Versal Device IP Added new section.
Recommendations for Different Versal Device Design Topologies Added new section.
Checking for Feedback Structures in Registers Updated example.
Check Inferred Logic Added information on retiming_forward and retiming_backward.
XPIO Global Clock Buffer Clock Enable Timing Added new section.
Boundary Clock Nets Removed example.
SSI Technology Considerations for I/O Planning Added new section.
Designing with SSI Devices Added new chapter.
Using the Boundary Logic Interface Constraint Added new section.
Floorplanning Constraints for Dynamic Function eXchange Added recommendations and revised entire section.
Assessing Post-Synthesis Quality of Results Updated table.
NoC Compiler Runs During Placement Added information on global placement.