hivec - 2022.1 English

Syntax

• For Zynq devices and Zynq UltraScale+ MPSoC:

  [hivec] <partition>

• For Versal® ACAP:

  { hivec, file=<partition> } 

Description

To specify the location of Exception Vector Table as hivec. This is applicable with a53 (32 bit) and r5 cores only.

• hivec: exception vector table at 0xFFFF0000.
• lovec: exception vector table at 0x00000000. This is the default value.

Arguments

None

Example

• For Zynq devices and Zynq UltraScale+ MPSoC:

  all:                                              
  {                                                 
      [bootloader, destination_cpu=a53_0] fsbl.elf  
      [destination_cpu=r5-0,hivec] app1.elf         
  }

• For Versal® ACAP:

  all:                                              
  {                                                 
     image                                          
     {                                              
       name = image1, id = 0x1c000001               
       { type=bootloader, file=plm.elf }            
       { type=pmcdata, file=pmc_cdo.bin }           
       { type=cdo, file=fpd_data.cdo }              
       { core=psm, file=psm.elf }                   
       { core=r5-0, hivec, file=hello.elf }         
     }                                              
  }