Stacked Silicon Interconnect Technology (SSI technology) is used to break through the limitations of Moore’s law and deliver the capabilities to satisfy the most demanding design requirements.
A SSI Technology device consists of multiple Super Logic Region (SLRs), where each SLR is one die. SLR0, also referred to as Master SLR, is the bottom die. SLR1 is second from bottom, SLR2 is third from bottom and so on. The Versal® ACAP SSI technology variants can have a maximum of four SLRs.
Each SLR has its own Platform Management Controller (PMC) and a Programmable Logic (PL) region like a monolithic Versal® ACAP device, but the slave SLRs do not have AI Engine (AIE) and Processing System (PS) regions.
The final PDI to boot on this device is a PDI of PDIs. Because each SLR has
its own PMC block, each SLR boots with a PDI which is integrated in the main PDI.
Note: PLM elf in each SLR should be
same.
The BIF for
Versal®
ACAP SSI technology
devices is different from its monolithic variant. Below is an example bif with two SLR
devices.
Note: The whole BIF code block below goes into a
Single file. Bootgen reads multiple BIF blocks and creates respective PDIs based on the BIF
labels. These BIF block labels are referenced in master BIF, based on which Bootgen merges
the individual PDIs into a master PDI. This master PDI alone is sufficient to boot an SSI
technology device
// For generating SLR1 – boot PDI
bitstream_boot_1:
{
id_code = 0x04d10093
extended_id_code = 0x01
id = 0xb
boot_config {smap_width=0}
image
{
name = pmc_subsys, id = 0x1c000001
partition { id = 0xb01, type = bootloader, file = gen_files/plm.elf }
partition { id = 0xb0A, type = pmcdata, load = 0xf2000000, file = gen_files/pmc_data_slr_1.cdo }
}
image
{
name = pl_noc, id = 0x18700000
partition { id = 0xb05, type = cdo, file = boot_1.rnpi }
}
}
// For generating SLR2 – boot PDI
bitstream_boot_2:
{
id_code = 0x04d10093
extended_id_code = 0x01
id = 0xb
boot_config {smap_width=0}
image
{
name = pmc_subsys, id = 0x1c000001
partition { id = 0xb01, type = bootloader, file = gen_files/plm.elf }
partition { id = 0xb0A, type = pmcdata, load = 0xf2000000, file = gen_files/pmc_data_slr_2.cdo }
}
image
{
name = pl_noc, id = 0x18700000
partition { id = 0xb05, type = cdo, file = boot_2.rnpi }
}
}
// For generating SLR1 – partial config PDI
bitstream_1:
{
id_code = 0x04d10093
extended_id_code = 0x01
id = 0xc
boot_config {smap_width=0}
image
{
name = pl_cfi, id = 0x18700000
partition { id = 0xc03, type = cdo, file = config_1.rcdo }
partition { id = 0xc05, type = cdo, file = config_1.rnpi }
}
}
// For generating SLR2 – partial config PDI
bitstream_2:
{
id_code = 0x04d10093
extended_id_code = 0x01
id = 0xc
boot_config {smap_width=0}
image
{
name = pl_cfi, id = 0x18700000
partition { id = 0xc03, type = cdo, file = config_2.rcdo }
partition { id = 0xc05, type = cdo, file = config_2.rnpi }
}
}
// For generating final PDI – by combining above generated PDIs.
bitstream_master:
{
id_code = 0x04d10093
extended_id_code = 0x01
id = 0x2
image
{
name = pmc_subsys, id = 0x1c000001
partition { id = 0x01, type = bootloader, slr = 0, file = gen_files/plm.elf }
partition { id = 0x09, type = pmcdata, load = 0xf2000000, slr = 0, file = gen_files/pmc_data.cdo }
}
image
{
name = SUB_SYSTEM_BOOT_MASTER, id = 0x18700000, type = slr-boot
partition { id = 0x05, type = cdo, slr = 0, file = boot_0.rnpi }
partition { id = 0xb15, slr = 1, section = bitstream_boot_1 }
partition { id = 0xb15, slr = 2, section = bitstream_boot_2 }
partition { id = 0x02, type = cdo, file = gen_files/bd_70da_pspmc_0_0_noc_clock.cdo }
}
image
{
name = lpd, id = 0x4210002
partition { id = 0x0C, type = cdo, slr = 0, file = gen_files/lpd_data.cdo }
partition { id = 0x0B, core = psm, slr = 0, file = static_files/psm_fw.elf }
}
image
{
name = fpd, id = 0x420c003
partition { id = 0x08, type = cdo, slr = 0, file = gen_files/fpd_data.cdo }
}
image
{
name = CONFIG_MASTER, id = 0x18700001, type = slr-config
partition { id = 0xc16, slr = 1, section = bitstream_1 }
partition { id = 0xc16, slr = 2, section = bitstream_2 }
partition { id = 0x13, type = cdo, slr = 0, file = master_config.rcdo }
}
}Note: MCS format bootimage/PDI generation is
not supported for Versal SSI technology devices.